Inside Arteris: Andy Nightingale on AI-Driven NoC Innovation and SoC Future

Andy Nightingale's Expertise in Semiconductor Innovation

Andy Nightingale, VP of Product Marketing at Arteris, brings over 35 years of experience in high-tech, blending engineering and product marketing expertise. His extensive career includes 23 years at Arm, where he contributed to ASIC test benches and product management. Currently, he leads product marketing for Arteris' cutting-edge system-on-chip (SoC) interconnect IP solutions.

The Evolving Role of Interconnect IP in SoC Design

Interconnect IP has transitioned from a fixed infrastructure to a strategic enabler for SoC scalability, power efficiency, and AI/ML performance. The emergence of chiplets, domain-specific accelerators, and multi-die architectures demands more adaptive, innovative, and intelligent interconnect technologies. Andy highlights how AI is now integrated into interconnect design to optimize Network-on-Chip (NoC) topologies, data routing, and congestion anticipation.

AI's Expanding Impact on Chip Design

Arteris' FlexGen exemplifies AI-driven automation in NoC topology generation. It uses machine learning to initialize floorplans, generate optimized topologies, configure clocks, and reduce clock domain crossings, delivering deterministic and replicable results. Over the next five years, AI is expected to evolve from a productivity tool to a co-designer in chip development, accelerating the delivery of AI-ready chips.

Challenges and Solutions in NoC Design for Advanced Architectures

The complexity of AI, HPC, and multi-die architectures presents scalability challenges for NoC design, especially managing diverse bandwidth, latency, and power requirements across multiple domains. FlexGen addresses these by minimizing wire length, maximizing bandwidth, and adapting to physical constraints with speed and repeatability. Automation and AI enable rapid design iteration and adaptation to late-stage changes.

FlexGen’s Advantages in AI Workload Support

FlexGen supports high-bandwidth, low-latency, and power-efficient NoC configurations tailored for AI workloads, including Generative AI and Large Language Models. Its incremental design and advanced pathfinding features allow dynamic optimization without full redesigns, critical for evolving AI chips. Arteris technology is already integrated into multi-die and chiplet systems, enhancing traffic routing while respecting floorplan and clock domain constraints.

Differentiation in RISC-V and Custom Silicon Interconnects

Unlike traditional fixed-function interconnects, Arteris provides configurable, scalable NoC IP designed to handle the modularity and diversity of modern SoCs, including RISC-V cores and custom accelerators. FlexGen’s topology optimization is workload-aware, supporting low-latency AI inference paths and high-bandwidth routes, enabling faster, risk-reduced custom silicon development.

Accelerating SoC Design with FlexGen Automation

FlexGen achieves a tenfold increase in design iteration speed by automating complex NoC design tasks. Its physically aware AI engine handles topology configuration, clock domain resolution, and routing optimization within hours, reducing time-to-market and improving design quality. Partial completion mode preserves manual design intent while accelerating timing closure.

Power Efficiency Through Wire Length Reduction

Reducing wire length by up to 30% lowers power consumption, latency, and heat generation, enhancing performance-per-watt — crucial for edge AI, mobile computing, and cloud AI workloads. FlexGen’s AI-guided placement and routing optimize performance targets without compromising power efficiency, supporting energy-sensitive designs.

Industry Adoption Across Diverse Markets

Arteris NoC IP and FlexGen are widely adopted in automotive, data centers, industrial electronics, and more. Automotive companies use FlexGen to meet AI and safety requirements in autonomous driving. Data centers benefit from managing massive bandwidth for AI training, while industrial sectors value rapid design cycles and long product lifespans supported by AI-based optimization and incremental design flows.

Resilience Amid Semiconductor Supply Chain Challenges

Arteris counters supply chain disruptions with flexible, automated NoC solutions compatible with various process nodes, IP vendors, and design environments. FlexGen enables agile design adjustments to silicon availability or packaging strategy changes, reducing dependency and ensuring project schedules remain intact.

Preparing for the Future of SoC Development

Arteris anticipates growing heterogeneity, chiplet-based designs, and AI-centric workloads requiring flexible, scalable, and intelligent interconnects. Investments in AI-driven automation, multi-die support, incremental design, and rapid iteration prepare Arteris and its customers to meet shrinking development cycles and rising complexity, delivering optimal power, performance, and area no matter the architecture or foundry.

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